C++ has gained support for the new RISC-V hardware platform

C++ Officially Adds Support for the RISC-V Architecture: What Does This Mean for Developers?

The world of programming languages continues to evolve. Earlier this month, the C++ Standards Committee (WG21) and the development teams of major compilers (GCC, Clang/LLVM) announced full official support for the open hardware architecture RISC-V in the current versions of C++17, C++20, and the upcoming C++23. This event marks a new stage in the development of a language traditionally considered the "king" of embedded systems and high-performance computing.

Previously, C++ already had experimental support for RISC-V, but it has now become stable. This means developers can use modern language features (templates, constexpr, coroutines, ranges) on microcontrollers, servers, and even supercomputers built on this architecture, without the risk of encountering undocumented compilation errors.

Why is RISC-V So Important for C++?

RISC-V is not just another processor. It is an open, modular architecture that any manufacturer can use without royalty fees. Unlike ARM or x86, where the ecosystem is tightly controlled by vendors, RISC-V offers complete freedom: from startups making IoT chips to government projects striving for technological independence.

For C++, this is an ideal environment:

• Low-level control. The language allows writing code that is as close to the "metal" as possible, and RISC-V has a simple and predictable instruction set.
• Scalability. From 8-bit microcontrollers (RV32E) to 64-bit multi-core systems (RV64GC) — C++ works everywhere.
• Security. The new C++20/23 standards add modules, concepts, and improved memory management, which is critical for RISC-V devices without complex MMUs.

What Specifically Changed?

The main innovations that have achieved "production-ready" status:

• GCC 13+ and Clang 16+: fully support RISC-V extensions (vector instructions V, compressed instructions C, atomic operations A).
• Standard Library: adapted for working with hardware timers, interrupts, and multithreading on RISC-V.
• Tooling: QEMU now has a reference RISC-V model with full GDB debugging support for C++.
• Operating Systems: Linux 6.x and FreeBSD for RISC-V fully support C++ applications (including std::thread, std::filesystem).

Practical Use Cases

Developers are already actively porting complex C++ frameworks to RISC-V:

• Game engines (Godot, Unity — experimentally).
• Machine learning libraries (TensorFlow Lite, ONNX Runtime).
• Cryptographic libraries (OpenSSL, Botan).

Of particular interest is the SiFive project, where full-fledged C++ applications with coroutines for asynchronous I/O in IoT networks are being run on RISC-V chips.

What's Next?

The C++ Committee has already announced working groups to optimize the ABI (Application Binary Interface) for RISC-V and to add standard hardware attributes (for example, for direct register access). It is expected that by 2025, RISC-V could